The present invention relates to semiconductor package assembly processes, and in particular, to chip scale package assembly methods.
As society progresses, there is a desire for smaller and thinner devices. One method of shrinking the electrical devices is to create more complex semiconductor chips that take up less real estate in the electronic device. Shrinking the semiconductor packaging may also help to achieve that goal. Traditional semiconductor packages have used a metal lead frame that provides electrical connections to the printed circuit board outside the package. The size of the traditional package is limited by the size of the lead frame.
The desire for miniaturization has pushed the development of advanced packaging methods such as chip scale packages (CSP). CSPs allow for a smaller package outline and footprint. Instead of using a lead frame like traditional semiconductor packages, a CSP uses metallization to generate contact pads of the semiconductor die for contact. Furthermore, the chip is generally encapsulated within a mold compound to protect the chip from the environment and prevent it from flexing. This allows the semiconductor chip package size to be close in size to semiconductor die itself. The reduction of packaging size allows for higher integration of electronics and therefore enables more enhanced functionality and allows for a reduction in overall size of the electronic device.
However, as compared to traditional packaging methods, the disadvantage of CSP is its higher manufacturing cost. Present chip scale package assembly methods require advanced processing techniques and special die layout in order to manufacture such products. Furthermore, current techniques may not sufficiently protect the semiconductor package unit from damage created by exposures to the environment such as damage by moisture, thereby reducing the service life of the package unit.
Thus, there is a need for improved package assembly methods. The present invention solves these and other problems by providing chip scale package assembly methods.